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CXD1177Q
8-bit 40MSPS YC 2-channel D/A Converter
Description The CXD1177Q is an 8-bit high-speed D/A converter for video band use. It has an input/output equivalent to 2 channels of Y and C. It is suitable for use of digital TV, graphic display, and others. Features * Resolution 8-bit * Maximum conversion speed 40MSPS * YC 2-channel input/output * Differential linearity error 0.3 LSB * Low power consumption 160 mW (200 load at 2 Vp-p output) * Single 5 V power supply * Low glitch noise * Stand-by function Structure Silicon gate CMOS IC 32 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage AVDD, DVDD 7 V * Input voltage (All pins) VIN VDD +0.5 to VSS -0.5 V * Output current (Every each channel) IOUT 0 to 15 mA * Storage temperature Tstg -55 to +150 C
Recommended Operating Conditions * Supply voltage AVDD, AVSS 4.75 to 5.25 V DVDD, DVSS 4.75 to 5.25 V * Reference input voltage VREF 2.0 V * Clock pulse width TPW1, TPW0 11.2 ns (min.) to 1.1 s (max.) * Operating temperature Topr -40 to +85 C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E90602F01
CXD1177Q
Block Diagram
(LSB) Y0 1 2LSB'S CURRENT CELLS 32 DVDD 31 AVDD
Y1 2 Y2 Y3 3 4 DECODER LATCHES
28 YO 6MSB'S CURRENT CELLS 29 YO
Y4 5 Y5 Y6 (MSB) Y7 (LSB) C0 6 7 8 9 DECODER
19 YCK CLOCK GENERATOR 2LSB'S CURRENT CELLS
23 AVSS 21 DVSS
C1 10 C2 11
26 C3 12 C4 13 C5 14 C6 15 (MSB) C7 16 BLK 17 CE 18 DECODER CLOCK GENERATOR CURRENT CELLS (FOR FULL SCALE) BIAS VOLTAGE GENERATOR DECODER LATCHES 6MSB'S CURRENT CELLS 27
CO CO
20 CCK 30 VG 25 VREF 24 IREF
22 VB
IREF
AVss
DVss
Pin Configuration
CCK
YCK
VB
24
23
22
21
20
19
18
CE
17
VREF CO CO YO
BLK
25 26 27 28
16 C7 15 C6 14 C5 13 C4 12 C3 11 C2 10 C1 9 C0
YO 29 VG 30 AVDD DVDD 31 32
1
2
3
4
5
6
7
8
Y1
Y3
Y5
Y0
Y2
--2--
Y4
Y6
Y7
CXD1177Q
Pin Description and I/O Pins Equivalent Circuit Pin No. Symbol I/O Equivalent circuit
DVDD
Description
1 to 8
Y0 to Y7
1
I 9 to 16 C0 to C7
to 16 DVSS
Digital input Y0 (LSB) to Y7 (MSB) C0 (LSB) to C7(MSB)
DVDD
17
BLK
I
17
DVSS
Blanking input. This is synchronized with the clock input signal for each channel. No signal at "H" (Output 0 V). Output condition at "L".
DVDD
DVDD
22
VB
O
22
Connect a capacitor of about 0.1 F.
DVSS
DVDD
19
YCK I
19 20
Clock input.
20
CCK
DVSS
21 23
DVSS AVSS
-- --
DVDD
Digital ground Analog ground
18
CE
I
18
DVSS
Chip enable input. This is not synchronized with the clock input signal. No signal (Output 0 V) at "H" and minimizes power consumption.
--3--
CXD1177Q
Pin No.
Symbol
I/O
Equivalent circuit
Description Connect a resistance 16 times "RIR" that of output resistance value "ROUT".
24
IREF
O
24 AVDD
AVDD
AVDD
25
VREF
I
AVSS 25 AVDD
Set full-scale output value.
AVSS
30
30
VG
O
AVSS
Connect a capacitor of about 0.1 F.
31 27
AVDD CO
--
AVDD
Analog power supply
27
29
YO O
29 AVSS AVDD
Current output. Voltage output can be obtained by connecting a resistance.
26
CO
26 28
Inverted current output. Normally dropped to analog ground.
AVSS
28 32
YO DVDD --
Digital power supply
--4--
CXD1177Q
Electrical Characteristics Item Resolution Conversion speed Integral non-linearity error Differential non-linearity error Output full-scale voltage Output full-scale ratio 1 Output full-scale current Output offset voltage Glitch energy Crosstalk Supply current Analog input resistance Input capacitance Digital input voltage Digital input current Setup time Hold time Propagation delay time CE enable time 2 CE disable time 2 1 2 Symbol n FCLK EL ED VFS FSR IFS VOS GE CT IDD ISTB RIN CI VIH VIL IIH IIL ts th tPD tE tD
(FCLK=40 MHz, AVDD=DVDD=5 V, ROUT=200 , VREF=2.0 V, Ta=25 C) Measurement conditions AVDD=DVDD=4.75 to 5.25 V Ta=-40 to +85 C Endpoint Min. Typ. 8 Max. Unit bit MSPS LSB LSB V % mA mV pV*s dB mA M pF V A ns ns ns ms ms
0.5 -2.5 -0.3 1.8 0
40 2.5 0.3 2.2 3.0 15 1
2.0 1.5 10 30 57
When "00000000" data input ROUT=75 When 1 kHz sine wave input When 14.3 MHz CE=L color bar data input CE=H VREF AVDD=DVDD=4.75 to 5.25 V Ta=-20 to +75 C AVDD=DVDD=4.75 to 5.25 V Ta=-20 to +75 C ROUT=75 ROUT=75 CE=HL CE=LH
32 1.2 1 9 2.4 0.8 -5 5 10 10 2 2 4 4 x 100 (%) 5
Full-scale voltage for each channel Full-scale voltage average value for each channels When the external capacitors for the VG pins are 0.1 F. Full-scale output ratio =
-1
Electrical Characteristics Measurement Circuit Analog Input Resistance Digital Input Current
}
Measurement Circuit
+5.25V
AVDD, DVDD
A
CXD1177Q
V
AVSS, DVSS
--5--
CXD1177Q
Maximum Conversion Velocity Measurement Circuit
8bit COUNTER with LATCH Y0 to Y7 1 to 8 C0 to C7 9 to 16 17 BLK 0.1 18 CE 22 VB DVss CLK 40MHZ SQUARE WAVE 19 YCK 20 CCK VG 30 0.1 VREF 25 IREF 24 3.3k AVss 1k AVDD
YO 29 200 AVss CO 27 200 AVss OSCILLOSCOPE
Setup Time Hold Time Glitch Energy
}
Measurement Circuit
8bit COUNTER with LATCH Y0 to Y7 1 to 8 C0 to C7 9 to 16 17 BLK 0.1 18 CE 22 VB DVss VG 30 0.1 VREF 25 19 YCK DELAY CONTROLLER 20 CCK IREF 24 1.2k AVss 1k AVDD YO 29 75 AVss CO 27 75 AVss DELAY CONTROLLER OSCILLOSCOPE
CLK 1MHZ SQUARE WAVE
Crosstalk Measurement Circuit
ALL "1" DIGITAL WAVEFORM GENERATOR Y0 to Y7 1 to 8 C0 to C7 9 to 16 17 BLK 0.1 18 CE 22 VB DVss CLK 40MHZ SQUARE WAVE 19 YCK 20 CCK VG 30 0.1 VREF 25 IREF 24 3.3k AVss 1k AVDD YO 29 200 AVss CO 27 200 AVss SPECTRUM ANALYZER
--6--
CXD1177Q
DC Characteristics Measurement Circuit
Y0 to Y7 1 to 8 CONTROLLER C0 to C7 9 to 16 17 BLK 0.1 18 CE 22 VB DVss CLK 40MHZ SQUARE WAVE 19 YCK 20 CCK
YO 29 200 AVss CO 27 200 AVss AVDD VG 30 VREF 25 IREF 24 3.3k AVss 0.1 1k DVM
Propagation Delay Time Measurement Circuit
FREQUENCY DEMULTIPLIER
Y0 to Y7 1 to 8 C0 to C7 9 to 16 17 BLK 0.1 18 CE 22 VB DVss
YO 29 200 AVss CO 27 200 AVss AVDD VG 30 0.1 VREF 25 1k OSCILLOSCOPE
CLK 10MHZ SQUARE WAVE
19 YCK 20 CCK
IREF 24 3.3k AVss
--7--
CXD1177Q
Description of Operation Timing Chart
CLK tPW1 tPW0
2V
ts th
ts th
ts th
DATA
tPD
100%
D/A OUT tPD tPD
50%
0%
I/O Chart (When full-scale output voltage at 2.00 V) Input code MSB LSB 11111111 : 10000000 : 00000000 Output voltage 2.0 V 1.0 V 0V
Y OUT C OUT 200 AVss AVss AVDD 1k AVss 24 3.3k 2 3 4 Y IN 5 6 7 (MSB) 8 20 CLOCK 19 18 17 DVss 23 AVss 22 0.1F 21 DVss
Application Circuit
200 AVss DVDD AVDD 0.1F 32 (LSB) 31 30 29 28 27
26
25
1
9 (LSB)
10
11
12
13
14
15
16 (MSB)
C IN
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
--8--
CXD1177Q
Notes on Operation * How to select the output resistance The CXD1177Q is a D/A converter of the current output type. To obtain the output voltage connect the resistance to the current output pins Y0, C0. For specifications we have; Output full scale voltage VFS = 1.8 to 2.2 [V] Output full scale current IFS = less than 15 [mA] Calculate the output resistance value from the relation of VFS = IFS x ROUT. Also, 16 times resistance of the output resistance is connected to reference current pin IREF. In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here please note that VFS becomes VFS = VREF x 16ROUT/RIR. ROUT is the resistance connected to the current output pins YO and CO while RIR is connected to IREF. Increasing the resistance value can curb power consumption. On the other hand glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. * Phase relation between data and clock To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. Be sure to satisfy the provisions of the setup time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. * Power supply and grand To reduce noise effects separate analog and digital systems in the device periphery. For the power supply pins, both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 F, as close as possible to the pin. * Latch up AVDD and DVDD have to be common at the PCB power supply source. This is to prevent latch up due to voltage difference between AVDD and DVDD pins when power supply is turned ON. * YO and IO pins The YO and IO pins are the inverted current output pins described in the Pin Description. The sums shown below become the constant value for any input data. a) The sum of the currents output form YO and YO b) The sum of the currents output form CO and CO However, the performances such as the linearity error of the inverted current output pin output current is not guaranteed.
--9--
CXD1177Q
Latch Up Prevention The CXD1177Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pin 31) and DVDD (Pin 32), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources
DVDD AVDD
31 AVDD +5V +5V C CXD1177Q
32 DVDD C DIGITAL IC
AVSS 23 AVSS
DVSS 21 DVSS
b. When analog and digital supplies are from a common source (i)
DVDD
31 AVDD +5V C CXD1177Q
32 DVDD C DIGITAL IC
AVSS 23 AVSS
DVSS 21 DVSS
(ii)
DVDD
31 AVDD +5V C CXD1177Q
32 DVDD C DIGITAL IC
AVSS AVSS 23
DVSS 21 DVSS
--10--
CXD1177Q
2. Example when latch up easily occurs a. When analog and digital supplies are from different sources
DVDD AVDD 31 AVDD +5V +5V C CXD1177Q 32 DVDD DIGITAL IC
AVSS AVSS 23
DVSS 21 DVSS
b. When analog and digital supplies are from common source (i)
DVDD AVDD 31 AVDD +5V C CXD1177Q DIGITAL IC 32 DVDD
AVSS AVSS 23
DVSS 21 DVSS
(ii)
DVDD AVDD 31 AVDD +5V CXD1177Q DIGITAL IC 32 DVDD
AVSS AVSS 23
DVSS 21 DVSS
--11--
CXD1177Q
Example of Representative Characteristics
200 AVDD=DVDD=5.0V VREF=2.0V RIR 16ROUT Ta=25C
Output full scale voltage VFS [V]
2.0
Glitch energy GE [pV*s]
100
1.0 AVDD=DVDD=5.0V ROUT=200 RIR=3.3k Ta=25C
0
1.0
2.0
100
200
Reference voltage VREF [V] Reference voltage vs. Output full scale voltage
Output resistance ROUT [] Output resistance vs. Glitch energy
Output full scale voltage VFS [V]
60 2.0
Crosstalk CT [dB]
50 AVDD=DVDD= 5.0V VREF=2.0V ROUT=200 RIR=3.3k Ta=25C
1.9 AVDD=DVDD= 5.0V VREF=2.0V ROUT=200 RIR=3.3k 0 -25 0 25 50 75
40
100k
1M
10M
Ambient temperature Ta [C] Ambient temperature vs. Output full scale voltage
Output frequency FO [Hz] Output frequency vs. Crosstalk
--12--
CXD1177Q
Package Outline
Unit : mm
32PIN QFP (PLASTIC)
9.0 0.2 + 0.3 7.0 - 0.1 24 17 + 0.35 1.5 - 0.15
0.1
25
16
32
9
+ 0.2 0.1 - 0.1
1 0.8 + 0.15 0.3 - 0.1
8 + 0.1 0.127 - 0.05 0 to 10
0.24
M
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 QFP032-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g
--13--
0.50
(8.0)

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